Jobs

TYLsemi is seeking a highly experienced Principal Engineer – STA to lead timing analysis and signoff for advanced ASIC/SOC designs, focusing on chiplet infrastructure IP for AI/HPC systems. This role involves driving timing closure across complex scenarios, defining timing constraints, and collaborating with various design teams to ensure successful tape-outs at advanced technology nodes. The ideal candidate will have 12+ years of experience in STA, expertise with Synopsys tools, and strong technical leadership skills to contribute to critical silicon infrastructure that powers AI.