Senior RTL Engineer Silicon RTL Santa Clara, CA Santa Clara, CA Full-time 200000 - 500000 Role Overview We are looking for a Senior RTL Engineer to help build Velaura’s next-generation Physical AI SoC. In this role, you will work closely with architects, performance modelers, software engineers, verification engineers, and physical design teams to transform innovative architectural concepts into production silicon. You will own significant portions of the design, drive microarchitectural decisions, and help deliver high-performance, power-efficient hardware that enables the next generation of intelligent physical systems. Role Overview We are looking for a Senior RTL Engineer to help build Velaura’s next-generation Physical AI SoC. In this role, you will work closely with architects, performance modelers, software engineers, verification engineers, and physical design teams to transform innovative architectural concepts into production silicon. You will own significant portions of the design, drive microarchitectural decisions, and help deliver high-performance, power-efficient hardware that enables the next generation of intelligent physical systems. Why Velaura? Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world. This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you. Equal Employment Opportunity and Accommodations Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans. Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

Responsilibities

● Own the design, implementation, and optimization of RTL for key portions of the Velaura SoC.

● Collaborate with architects to develop robust and efficient microarchitectures, and drive microarchitectural decisions within your areas of ownership.

● Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.

● Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.

● Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.

● Optimize designs for performance, power, area, scalability, and reliability.

● Partner closely with verification and physical design teams throughout the development cycle, and mentor junior engineers on design methodology and microarchitecture.

● Analyze performance bottlenecks and propose architectural and implementation improvements.

● Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.

● Participate in and lead design reviews, contributing to a culture of technical excellence.

Required Qualifications

● 8+ years (or equivalent depth) designing RTL for complex digital systems, with demonstrated ownership of significant blocks or subsystems through tapeout.

● Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.

● Expert-level Verilog/SystemVerilog and modern RTL design methodologies (lint, CDC, synthesis-aware coding, low-power intent).

● Strong grasp of performance, power, and area tradeoffs, and experience making data-driven microarchitecture decisions.

● Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.

● Experience with hardware/software co-design and system-level performance optimization.

● Strong debugging and problem-solving skills.

● Ability to work effectively in — and technically lead within — a collaborative, multidisciplinary engineering environment.

Preferred Qualifications

● Deep expertise in memory subsystem design: caches, coherency, memory controllers (e.g., LPDDR/DDR/HBM), on-chip SRAM organization, address translation, and memory protection.

● Hands-on experience designing or significantly extending DMA engines, data-movement accelerators, or similar high-bandwidth data-path logic —including descriptor-based DMA, multi-channel arbitration, QoS, and outstanding-transaction management.

● Working knowledge of standard interconnect and coherency protocols (e.g., AXI, CHI, ACE) and their performance implications.

● Experience with SMMU/IOMMU design or integration, virtualization, and DMA isolation for safety or security.

● Familiarity with RAS features in memory and data paths, such as ECC, poisoning, and error reporting.

● Experience with NoC fabrics, virtual channels, and QoS mechanisms for memory traffic.

● Knowledge of functional safety (e.g., ISO 26262/ASIL) as it applies to memoryand data-path design.

● Experience with AI, machine learning, or edge AI hardware, especially tensordata-movement patterns and tiling strategies.

● Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.

● Knowledge of low-power design techniques and power management architectures.

● Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.

● Experience using modern AI tools and workflows to accelerate engineering productivity.

● Background in CPUs and memory subsystems, GPUs, AI accelerators,networking and communications silicon, storage and data movementarchitectures, robotics and autonomous systems, automotive and advanced driver-assistance systems (ADAS), aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.

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