Jobs

Efficient is seeking a Lead RTL Design Engineer to drive the microarchitecture definition and RTL implementation for their next-generation, ultra-low-power SoC. This role involves owning critical aspects like dataflow execution fabric, memory subsystems, and low-power logic, collaborating across architecture, DV, and physical design teams. The ideal candidate will have 8+ years of RTL design experience with tape-out ownership, deep SystemVerilog proficiency, and a strong understanding of parallel execution models. This is a unique opportunity to influence product development in a newly formed hardware engineering organization, shaping the future of energy-efficient computing at the edge.