Jobs

TYLsemi is seeking a PCIe Subsystem RTL Lead to drive the microarchitecture, integration, and implementation of PCIe subsystems for next-generation chiplet-based SoCs in AI/HPC. This role involves owning the PCIe subsystem from PHY to Transaction Layer, leading third-party IP integration, and defining critical aspects like power management and silicon bring-up. The ideal candidate will have 10+ years of digital IC design experience with deep expertise in PCIe architecture and strong SystemVerilog RTL skills. Join a fast-paced, high-impact team building the foundational chiplet infrastructure for the exploding AI market.