PD - Principal, Physical Design Engineering Bay Area Bay Area Full-time Join the leading chiplet startup! As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PnR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits. Join the leading chiplet startup! As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PnR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits. Responsibilities:

Architecture and packaging driven floorplanning and integration so physical partitions match system and package constraints

Well defined boundaries with lego style pin alignment and consistent interface placement across chip and blocks

Feedthrough, repeater and bus planning with early reservation of routing corridors, layers, and resources for cross block connectivity.

Define clocking architecture methodology selecting spine and rib, H tree, or mesh to optimize power, skew, latency, and robustness.

Establish CTS methodology including skew and latency targets, buffer and ICG strategy, NDR and shielding rules for critical clock routes.

Define skew groups and balancing strategy across library corners, ensuring consistent behavior under MMMC variations and derates.

Drive clock constraint quality across hierarchy with clean chip to block and block to chip handoff for signoff readiness.

Define DRC aware power grid architecture including rings, straps, and mesh, matching metal resistivity assumptions to IR drop targets and EM limits.

Ensure careful planning around analog routing with keepouts, shielding, spacing, and grid topology choices that preserve sensitive nets and meet DRC.

Drive lego aligned power mesh alignment across top level, subsystem, and block level with consistent strap pitch, via patterns, and clean connectivity.

Lead early and signoff EM and IR analysis, identify hotspots, and implement grid reinforcement and via optimization without routing or congestion penalties.

Align power planning with floorplan and package constraints including bump map, current demand, and entry points to minimize noise and IR drop.

Qualifications:

8 to 12 years ASIC physical design experience owning floorplanning integration clocking and power planning from early feasibility through signoff and tapeout on complex SoCs

Expert in architecture and package driven hierarchy planning with lego aligned boundaries pin strategy feedthrough repeater bus planning plus CTS methodologies including spine rib H tree or mesh

Strong EM IR PV and STA awareness with MMMC and library corner skew group balancing advanced node exposure TSMC 3nm 2nm or Samsung 2nm and functional ECO execution experience

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