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Principal ASIC Design Verification Engineer
Principal ASIC Design Verification Engineer
K2 SpaceAbout the role
K2 is seeking a Principal ASIC Design Verification Engineer to ensure the functionality, performance, and robustness of custom silicon designs for their high-power satellites. This hands-on role involves defining verification approaches, building SystemVerilog/UVM test benches, and driving constrained-random testing strategies. The ideal candidate will have 10+ years of experience in ASIC/SoC verification, a strong understanding of hardware design flows, and proficiency with various simulation and scripting tools. You will collaborate closely with cross-functional teams to shape first-generation silicon and advance DV methodologies.
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