Jobs

TYLsemi is seeking an experienced Staff Engineer – Static Timing Analysis (STA) to lead timing analysis and signoff for complex SoC and advanced-node designs. This role involves driving timing closure across multiple blocks and full-chip designs, collaborating with cross-functional teams, and enhancing STA methodologies. The ideal candidate will have 7+ years of experience in STA, strong expertise in timing signoff, MMMC analysis, and hands-on experience with Synopsys PrimeTime. Join a fast-paced, global team building critical chiplet infrastructure IP for the exploding AI/HPC market.