Senior Design Verification Engineer – Physical AI Compute Silicon DV Santa Clara, CA Santa Clara, CA Full-time 200000 - 500000 Role Overview We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC. In this role, you will work closely with architects, RTL engineers, software engineers, and system teams to verify complex hardware blocks and system-level behavior across the entire platform. You will help establish confidence in the correctness, performance, reliability, and safety of the architecture—from individual RTL blocks to complete HW/SW systems running real-world workloads. We welcome engineers at all experience levels who enjoy understanding systems, finding corner cases, and solving challenging technical problems. Role Overview We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC. In this role, you will work closely with architects, RTL engineers, software engineers, and system teams to verify complex hardware blocks and system-level behavior across the entire platform. You will help establish confidence in the correctness, performance, reliability, and safety of the architecture—from individual RTL blocks to complete HW/SW systems running real-world workloads. We welcome engineers at all experience levels who enjoy understanding systems, finding corner cases, and solving challenging technical problems. Why Velaura? Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world. This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you. Equal Employment Opportunity and Accommodations Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans. Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

Responsibilities

● Develop and execute verification strategies for key portions of the Velaura SoC.

● Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies.

● Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.

● Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.

● Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.

● Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.

● Develop assertions, checkers, scoreboards, and automated verification infrastructure.

● Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.

● Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.

● Post-silicon debug and root cause analysis.

● Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.

● Contribute to a culture of technical excellence and continuous improvement.

Required Qualifications

● 10+ Years of experience verifying complex digital systems.

● Strong analytical and problem-solving skills.

● Strong understanding of computer architecture, microarchitecture, SoC architecture and digital design fundamentals.

● Experience in understanding low power methodologies and verification criteria.

● Strong understanding of CDC issues, clocking and reset verification.

● Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies.

● Familiarity with formal verification techniques and tools.

● Experience with emulation, FPGA prototyping, or pre-silicon validation environments.

● Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures.

● Experience debugging complex system-level issues.

● Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Preferred Qualifications

● Experience with one or more of the following standards: ISO 26262, IEC 61508, IEC 61511, ISO 13849

● Experience with AI, machine learning, or edge AI hardware.

● Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.

● Experience verifying QoS, latency-sensitive, or real-time systems.

● Experience with HW/SW co-verification and system-level validation.

● Exposure to performance modeling, profiling, and workload characterization.

● Experience using modern AI tools and workflows to accelerate engineering productivity.

● Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and ADAS platforms, aerospace and defense systems,
real-time and safety-critical computing, or functional safety architectures and methodologies.

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