Jobs

TYLsemi is seeking a highly skilled Senior Engineer – Static Timing Analysis (STA) to join their Physical Design team, focusing on chiplet infrastructure IP for AI/HPC systems. This role involves driving timing closure and signoff for complex SoC designs across advanced technology nodes, collaborating with various design teams. The ideal candidate will have 5+ years of experience in STA, strong fundamentals, and hands-on experience with Synopsys PrimeTime. You will be instrumental in ensuring robust timing convergence and successful tapeout delivery for critical AI infrastructure.