Functional Safety Architect, Physical AI SoC Silicon Architecture Santa Clara, CA Santa Clara, CA Full-time 200000 - 500000

Responsibilities

Own the SoC functional safety architecture: define safety goals, safety mechanisms, and the hardware/software fault-handling strategy across Velaura’s Physical AI silicon roadmap.

Lead safety analyses—hazard analysis and risk assessment, DFMEA, FMEDA, FTA, and dependent-failure/common-cause analysis—and derive the quantitative safety metrics required by the target standard (SPFM, LFM, and PMHF for ISO 26262 ASIL; SFF, diagnostic coverage, HFT, and PFH/PFD for IEC 61508 SIL), including diagnostic-coverage targets for the SoC and its subsystems.

Define safety mechanisms for compute, AI/NPU, memory, and interconnect including error detection and correction, lockstep, BIST, and safe-state handling, and specify the assumptions of use for the safety element out of context (SEooC).

Partner with silicon design, firmware, safety, and platform software teams to embed safety requirements into the RTL, boot flow, and SDK, and to review implementations against the safety concept.

Own the safety case and work products across the safety lifecycle, coordinating with assessors and customers to support certification and audits.

Establish functional safety processes, standards, and design practices; mentor engineers and raise the safety-engineering bar across the organization.

Manage the interface between functional safety and adjacent disciplines—cybersecurity, reliability, and SOTIF—so that safety concerns are addressed holistically.

Required Qualifications

10+ years in functional safety or safety-critical hardware engineering, with significant experience taking silicon or embedded platforms through a full safety lifecycle.

Deep expertise with functional safety standards across frameworks—ISO 26262 (including part 11 for semiconductors) up to ASIL D and IEC 61508 up to SIL 3—and their application to SoC development, including the architectural constraints, hardware metrics, and systematic-capability requirements each imposes.

Hands-on experience leading safety analyses (HARA, FMEA/FMEDA, FTA, DFA) and computing hardware architectural metrics (SPFM, LFM, PMHF).

Strong command of hardware safety mechanisms—ECC, lockstep, BIST, redundancy, and safe-state design—and of the interface between RTL/silicon design, firmware, and low-level platform software.

Proven ability to build and defend a safety case and to drive safety requirements across multi-disciplinary teams from architecture through production.

Bachelor’s or advanced degree in Electrical/Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

Excellent written and verbal communication skills, with a track record of influencing technical direction and mentoring engineers.

Preferred Qualifications

Experience with functional safety for AI/ML accelerators or NPUs, and with SOTIF (ISO 21448) for autonomous and perception systems.

Familiarity with robotics, automotive, industrial, or other safety-critical domains, and with adjacent standards such as ISO/SAE 21434 (cybersecurity) or IEC 61508 derivatives.

Certification such as a recognized Functional Safety Engineer credential, and experience interfacing directly with certification bodies or assessors.

Prior experience at an early-stage or high-growth semiconductor or hardware company, building safety functions and processes from the ground up.

Master’s or Ph.D in Electrical/Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

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