Jobs

Eridu is seeking an experienced RTL Engineer to join their ASIC Engineering team in Saratoga, CA, focusing on cutting-edge Networking ASICs for AI data centers. This role involves defining, architecting, and implementing high-speed networking chips, with a focus on packet buffering, queuing, scheduling, and performance optimization. The ideal candidate will have 8-15 years of experience, mandatory hands-on knowledge of SystemVerilog and Verilog, and expertise in ASIC design methodologies and QoS mechanisms. This is a unique opportunity to shape the future of AI Networking and contribute to groundbreaking technology that accelerates AI performance.