Principal Packaging Engineer Platform Package Santa Clara, CA Santa Clara, CA Austin, Texas Bangalore Boston, MA Full-time 200000 - 500000 Role Overview We are looking for a Principal Packaging Engineer to own package architecture and development for Velaura’s next-generation SoCs. This role will lead packaging from concept through production, working across silicon, board, system, thermal, mechanical, and manufacturing teams to deliver high-performance, cost-effective, and manufacturable products. The ideal candidate has deep experience with advanced semiconductor packaging, package-level signal and power integrity, substrate and assembly technologies, and cross-functional system optimization. Role Overview We are looking for a Principal Packaging Engineer to own package architecture and development for Velaura’s next-generation SoCs. This role will lead packaging from concept through production, working across silicon, board, system, thermal, mechanical, and manufacturing teams to deliver high-performance, cost-effective, and manufacturable products. The ideal candidate has deep experience with advanced semiconductor packaging, package-level signal and power integrity, substrate and assembly technologies, and cross-functional system optimization. Why Velaura? Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world. This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you. Equal Employment Opportunity and Accommodations Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans. Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

Responsibilities

● Own package architecture from concept through production for Velaura SoCs.

● Partner with architecture and silicon teams to co-optimize package, die, board, and system design for performance, power, cost, and manufacturability.

● Drive package technology selection, including flip-chip, advanced substrates, fan-out, and future multi-die integration approaches.

●Lead package design, bump planning, substrate definition, escape routing, and assembly interactions with OSAT and substrate vendors.

● Own package-level signal integrity and power integrity planning for high-speed interfaces including LPDDR, PCIe, Ethernet, and other high-speed I/O.

●Collaborate on thermal architecture, mechanical integration, reliability, DFM, and qualification.

●Work with foundry, assembly, substrate, and test partners to successfully deliver products to production.

●Help define Velaura's long-term packaging roadmap as future products evolve.

Required Qualifications

●Deep experience developing advanced semiconductor packages for high-performance SoCs.

●Strong understanding of package architecture, substrate technologies, bumping, assembly flows, and manufacturing.

●Experience co-optimizing package design with silicon, board, SI/PI, thermal, and mechanical teams.

●Hands-on experience with signal integrity, power integrity, thermal, and reliability

considerations in advanced packages.

●Ability to balance technical excellence with cost, yield, manufacturability, and schedule.

●Excellent communication skills and a collaborative, first-principles engineering mindset.

Preferred Qualifications

● Advanced packaging technologies including chiplets, 2.5D integration, silicon bridges, or heterogeneous integration.

● HBM integration and high-bandwidth memory package architecture.

● Advanced process nodes (N3, N2, or beyond).

● Experience working with leading foundries, OSATs, and substrate vendors.

● Experience in an early-stage semiconductor company.

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