Jobs

TYLsemi is seeking a Principal SoC RTL Design Engineer to develop high-performance, scalable, and power-efficient digital designs for next-generation SoCs and Chiplets in AI, HPC, and Networking. This role requires deep expertise in RTL design, micro-architecture, and the integration of high-speed interfaces like PCIe/CXL, Ethernet, and UCIe. The ideal candidate will have 8+ years of experience in Verilog/SystemVerilog and a strong focus on quality and first-time silicon success. Join a fast-paced, global team building critical chiplet infrastructure IP for the exploding AI market.