Jobs

Kandou is seeking a Lead Analog Layout Engineer to work on custom layout and verification of analog circuits for multi-Gigabit high-speed communication links. This role involves expertise in high-speed/frequency circuit layout, including SerDes up to 28Gb/s, in advanced semiconductor technology nodes like 28nm, 14/16nm, and 7nm. The ideal candidate will have experience with EDA tools such as Cadence Virtuoso and Calibre/PVS, and a strong understanding of layout techniques for high-speed circuits. You will interact closely with design teams and customers, supporting IP and chip-level integration.