Custom Characterization Engineer (Staff) Silicon Custom Design Bangalore Bangalore Full-time 3500000 - 6500000

Responsibilities

● Own the characterization and quality assurance of standard cell libraries across advanced technology nodes, including FinFET and Gate-All-Around (GAA).

● Develop, improve, and optimize standard cell characterization methodologies to deliver high-quality timing, power, and noise models.

● Generate and validate Liberty (.lib) views including NLDM, CCS, ECSM, and LVF models, with silicon and hardware correlation.

● Develop and maintain characterization, simulation, regression, and automation flows to improve productivity and model quality.

● Perform statistical verification and Monte Carlo analysis using Solido, Spectre FMC, or accelerated sigma simulation methodologies.

● Collaborate with circuit and layout teams to optimize standard cells for performance, power, area (PPA), layout-dependent effects (LDE), coloring compliance, and pin accessibility.

● Drive innovative characterization solutions aligned with Velaura AI's technology roadmap and customer requirements.

● Partner with Circuit Design, Physical Design, STA, CAD, and Product Engineering teams to deliver high-quality library releases.

Required Qualifications

● 5+ years of experience in characterization of standard cell libraries for advanced process technologies.

● Hands-on experience with deep submicron, FinFET, and GAA technologies.

● Expertise in Liberty model generation and validation, including NLDM, CCS, ECSM, and LVF.

● Experience developing characterization automation, regression, and quality assurance frameworks.

● Proficiency with circuit simulation tools such as HSPICE, PrimeSim XA, or Spectre.

● Experience with statistical characterization and Monte Carlo simulation methodologies.

● Exposure to parasitic extraction using StarRC or Quantus.

● Working knowledge of transistor-level standard cell circuit design and optimization.

Preferred Qualifications

● Master's degree in Electrical Engineering, Electronics Engineering, or a related field.

● Understanding of transistor-level circuit design and PPA optimization for standard cells including latches, flip-flops, multiplexers, AOI/OAI, XOR/XNOR, encoders, decoders, level shifters, and arithmetic cells.

● Strong understanding of Layout Dependent Effects (LDE), advanced-node device physics, and manufacturing-aware design.

● Good understanding of Static Timing Analysis (STA), Liberty (.lib) modeling, and flip-flop timing.

● Knowledge of ASIC implementation and sign-off methodologies.

● Programming and automation experience using Python, Tcl, or Perl.

● Experience with low-power library characterization and advanced Liberty modeling features.

● Exposure to custom circuit design and standard cell layout optimization.

● Excellent communication, collaboration, analytical, and problem-solving skills, with a strong sense of ownership and the ability to deliver under demanding project schedules.

● Background in standard cell characterization and library development; timing, power, and noise model generation; advanced-node technologies including Deep Submicron, FinFET, and GAA; or statistical characterization and model
validation.

Jobs

No opportunities available

Browse Jobs by Role

Browse Jobs by City