Jobs

Upscale AI is seeking a highly technical, hands-on Principal DV Engineer to lead the verification of their next-generation, high-performance networking silicon. This role involves anchoring the verification of complex IPs and critical sub-systems, balancing advanced architectural environment creation with rigorous execution. The ideal candidate is a veteran engineer with 15+ years of ASIC/SoC Design Verification experience, mastery of System Verilog and UVM, and extensive domain expertise in networking. You will be responsible for the complete verification lifecycle, architecting UVM environments, driving test planning, and serving as the team's expert for debugging hardware bugs.