Jobs

TYLsemi is seeking a Principal Mixed Signal RTL Design Engineer to lead the micro-architecture and RTL design for mixed-signal chiplets, focusing on intelligent power optimization for AI and HPC. This role involves architecting and implementing digital control loops, translating MATLAB/Simulink models to production-quality RTL, and collaborating with analog designers. The ideal candidate will have a strong mixed-signal background, proven experience with RTL design for control algorithms, and 8+ years in power management ICs or high-performance mixed-signal design. Join a fast-paced team building critical chiplet infrastructure IP for the exploding AI market.