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Senior Principal Engineer - Design Verification
Senior Principal Engineer - Design Verification
Upscale AIUpscale AI is seeking a visionary Senior Principal DV Engineer to define and govern the global verification strategy for massive-scale networking SoCs. This elite technical leadership role involves pioneering next-generation verification technologies like Formal and Emulation, influencing design architectures for verifiability, and serving as a strategic advisor to executive leadership. The ideal candidate will have 15-17+ years of distinguished ASIC/SoC Verification experience, deep networking domain knowledge, and expertise in System Verilog and UVM. This high-impact position offers the opportunity to drive methodology innovation and ensure zero-defect silicon for critical AI infrastructure.
